1. Field of the Invention
The invention relates to a semiconductor device provided with a regulator circuit on a semiconductor substrate requiring phase compensation.
2. Description of the Related Art
A regulator circuit is generally configured, for example, by a circuit shown in FIG. 1.
The regulator circuit shown in FIG. 1 is configured by a transistor MPO, two voltage divider resistor elements RA (first voltage divider resistor element), RB (second voltage divider resistor element), a differential amplifier 11 (differential operational amplifier element), and a phase compensation capacitor C1.
The transistor MPO is connected to nodes N1, N4 and N5 such that a source and a back bias thereof are connected to the source power supply node N1 (power supply terminal), a gate thereof is connected to the node N4 (differential output terminal of the differential operational amplifier element) and a drain thereof is connected to the regulator voltage output node N5 (output terminal of the transistor MPO), wherein a specific output voltage is outputted to the node N5 based on an input voltage inputted from the node N1.
The first voltage divider resistor element RA is connected to nodes N3 and N5 such that one terminal thereof is connected to the node N3 (non-inverting input terminal of the differential operational amplifier element) and the other terminal thereof is connected to the node N5 (output terminal). The second voltage divider resistor element RB is connected to the node N3 and a GROUND node such that one terminal thereof is connected to the node N3 and the other terminal is connected to the GROUND node (ground terminal). These voltage divider resistor elements RA and RB are connected to each other in series between the node N5 and the GROUND node.
The differential amplifier 11 is connected to the nodes N2 and N3 such that a differential input thereof is connected to the node N2, namely, reference voltage input node N2 (inverting input terminal) and an output thereof is connected to the node N4 (differential output terminal of the differential operational amplifier element). Further, a power supply of the differential amplifier 11 is connected to the source power supply node N1 (power supply terminal) and a current power supply thereof is connected to a source current node N6. The differential amplifier 11 receives a reference voltage and a voltage divided by the voltage divider resistor elements RA and RB from the nodes N2 and N3, and a signal representing the input voltage is differentially amplified, which is in turn outputted to the gate of the transistor MPO through the node N4, thereby controlling an output voltage of the transistor MPO.
The phase compensation capacitor C1 is connected between the nodes N4 and N5, namely, the regulator voltage output node N5.
The regulator circuit of the invention starts operation when a voltage is supplied to the nodes N1, N2 and a current is supplied to the node N6. The differential amplifier 11 outputs a voltage which is lower than a threshold voltage of the transistor MPO if the potential of the node N3 is lower than that of the node N2 while it outputs a voltage which is higher than the threshold voltage of the transistor MPO if the potential of the node N3 is higher than that of the node N2, thereby controlling the gate of the transistor MPO. Since the differential amplifier 11, the transistor MPO and the first voltage divider resistor element RA constitute a feedback loop, the potential of the node N3 converges on a potential which is the same as that of the node N2, and a fixed voltage which is decided by a ratio between the resistances of the voltage divider resistor elements RA and RB is outputted to the node N5.
The phase compensation capacitor C1 compensates a phase lag caused by a response lag of each component constituting the feedback loop, namely, response lag in the differential amplifier 11, the transistor MPO and the first voltage divider resistor element RA, and it is disposed between the nodes N4 and N5, thereby serving to loose no time in transmitting the response of the node N4 to the node N5. As a result, the response lag in the transistor MPO is cancelled, thereby preventing oscillation thereof.
However, as shown in FIG. 2, the conventional semiconductor device has a problem that layout areas of the components thereof become large because the voltage divider resistor elements RA and RB, the differential amplifier 11, the transistor MPO, and the phase compensation capacitor C1 are disposed in independent layout areas, wherein the layout area of the phase compensation capacitor C1 is provided separately from those of the other components.
There is proposed a semiconductor device wherein a capacitor is overlaid two-dimensionally on a resistor element in order to improve the increase of layout areas of the components of the semiconductor device, for example, as disclosed in JP-A 05-090502. According to this proposal, a capacitor overlaid two-dimensionally on a resistor element constituting an RC filter circuit, thereby improving the increase of layout areas of the components, thereby rendering the semiconductor device small in chip.
Meanwhile, even in a regulator circuit of the semiconductor device, it is considered to improve the increase of layout areas of the components in the same manner set forth above, however, this regulator circuit has a problem of security of a phase margin of the phase compensation capacitor (capacitor element) which is overlaid two-dimensionally on a resistor element. If the phase margin of the phase compensation capacitor is lowered, the phase compensation of the regulator circuit is not satisfactorily effected, arising a problem of generation of oscillation of the regulator circuit.